CODEWITHSUNDEEP
vhdlsimulationsystem-verilogmodelsimquestasim
Edu Fer
Edu Fer

Reputation: 9

Error using a VHDL function inside package into a systemverilog module. Mixed VHDL - SystemVerilog -mixedsvvh example

I present the VHDL & SystemVerilog code, of a very simple example.

I would like to know if it's possible to do what I am trying. And in case it is, why I am getting an error Considered I am using Questasim this is the code:

my_package.vhd

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package my_package is
    -- Type declarations
    type my_array is array (0 to 3) of std_logic_vector(7 downto 0);

    -- Constant declarations
    constant MY_CONSTANT : std_logic_vector(7 downto 0) := "10101010";

    -- Function declarations
    function add(a, b: std_logic_vector(7 downto 0)) return std_logic_vector;
end package my_package;

package body my_package is
    function add(a, b: std_logic_vector(7 downto 0)) return std_logic_vector is
    variable result : std_logic_vector(7 downto 0);
    begin
        result := std_logic_vector(unsigned(a) + unsigned(b));
        return result;
    end function;
end package body my_package;

sv_module.sv

    // Import VHDL package and its contents
    import my_package::*;
    

module sv_module;
    
    
    logic [7:0] a, b, result;

    initial begin
        a = 8'h05;
        b = 8'h03;
        result = add(a, b);
        $display("Result of VHDL add: %h", result);
    end
endmodule

I tried to compile both of them by: `vcom -mixedsvvh -work ../my_lib ../vhd_source/my_package.vhd

vlog -mixedsvvh -work ../my_lib ../sv_source/sv_module.sv`

Is it possible what I am trying to do? I would like to know why compiling sv_module.sv, is only possible if I use as destination library the same folder as for my_package.vhd, ../my_lib. Otherwise I get the error: vlog-13006 Could not find the package And also I would like to know why, afterwards when trying to simulate, I get the error : Error (suppressible): ../sv_source/sv_module.sv(13): (vopt-7063) Failed to find 'add' in hierarchical name 'add'.

Regards.

Upvotes: -2

Views: 103

Answers (1)

dave_59
dave_59

Reputation: 42738

It is not currently possible to procedurally call a procedure defined in one HDL language directly from another HDL language. Questa's -mixedsvvh switch is for sharing type information when connecting ports at mixed HDL port boundaries.

Upvotes: -1

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