CODEWITHSUNDEEP
verilogsystem-verilogsynopsys-vcs
Mery Karapetyan
Mery Karapetyan

Reputation: 11

Arithmetic logic unit (ALU) syntax error: token is '['

Error-[SE] Syntax error
  Following verilog source has syntax error :
  "alu_tb.v", 4: token is '['
     logic [31:0] A;

I hope to find a solution.

I changed the brackets.

I changed the comma and the letter.

Upvotes: 1

Views: 66

Answers (2)

Greg
Greg

Reputation: 19112

By default, simulators will parse .v files as IEEE1364 Verilog files and .sv as IEEE1800 SystemVerilog files. Flags like VCS's -sverilog (other simulators have their own flags) will forces the simulator to parse .v as IEEE1800 SystemVerilog files. It is okay to use the flag as a quick solution, but it is not the recommended long-term solution.

The preferred solution is to change the file extension of your SystemVeilog files from .v to .sv. This allows your simulator to mix SystemVerilog and legacy Verilog files with reduced risk of keyword conflicts. There are plenty of standard cell libraries written in Verilog that use variables names that are keywords in SystemVerilog. Using the correct file extension will also help your text editor with syntax highlighting.

In summary: Rename alu_tb.v to alu_tb.sv

Upvotes: -1

toolic
toolic

Reputation: 62236

logic is a keyword added to the IEEE Std 1800 for SystemVerilog (SV); this keyword was not available in the old Std 1364 for Verilog.

Many simulators do not enable SV features by default. Your error message looks like it comes from the Synopsys VCS simulator, which does not enable SV by default.

To enable SV, use the -sverilog option to the vcs command:

vcs -sverilog

To get vcs usage help, use this command:

vcs -h

Here is the description of this option:

-sverilog
   Enables the use of the Verilog language extensions in the Accellera
   SystemVerilog specification.

When using this option, the error is fixed.

Upvotes: 1

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