CODEWITHSUNDEEP
vhdlfixed-point
vipin
vipin

Reputation: 1660

fixed point conversion from a real variable in vhdl

I have the following code snippet in vhdl:

signal s: signed(31 downto 0);
s <= to_signed(to_sfixed(1.2,8,-23),32);

Now I am expecting the fixed point version of 1.2 to be available in the signal 's'.

But it always neglects the fraction part. The 's' just contains the decimal part(here "1").

What am I missing here?

Upvotes: 0

Views: 5402

Answers (2)

wjl
wjl

Reputation: 7755

If you just want to reinterpret the bits from the sfixed to as signed type, just use a simple type conversion:

signal s: signed(31 downto 0);
...
s <= signed(to_sfixed(1.2,8,-23));

Upvotes: 1

Martin Thompson
Martin Thompson

Reputation: 16792

s doesn't have anywhere to store any fractional part, it's a signed vector which can only represent integers.

You're nearly there though - drop the signedness and make s and sfixed type:

signal s: sfixed(8 downto -23);
s <= to_sfixed(1.2,sfixed'high,sfixed'low);

Upvotes: 1

Related Questions