CODEWITHSUNDEEP
mipscpu-architecturemips32
user379888
user379888

Reputation:

Finding offset from a code snippet

I am a bit stuck up with the following question,

Consider the following MIPS code and answer the questions that follow.

addi $t1, $s0, 400
loop: lw $s1, 0($s0)
add $s2, $s2, $s1
lw $s1, 4($s0)
add $s2, $s2, $s1
addi $s0, $s0, 8
bne $t1, $s0, loop

What value is the label loop translated to in the conditional branch instruction?

Now I know the mathematical formula for Branch Target Address. But here as memory addressing is not done so I found out the offset by counting the lines between the target address and PC. This gives the answer to be 7 (word offset). Am I right with this approach?

Upvotes: 2

Views: 912

Answers (2)

Vladimir F Героям слава
Vladimir F Героям слава

Reputation: 60008

A quick experiment with MARS simulator http://courses.missouristate.edu/KenVollmar/MARS/download.htm gave me the answer-6, -5 for number of lines difference and another -1 because PC is increased by 1 after the instruction.

Upvotes: 2

m0skit0
m0skit0

Reputation: 25873

AFAIK, I'm afraid not.

As MIPS instruction reference says:

An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.

So as I understand, the distance from the branch instruction to the loop label is negative (because the label is before the branch, thus the address is lower). The distance is calculated in number of words (hence the 2 bits left shift). As all MIPS instructions are 4 bytes, this would be 6 instructions before, hence -6 is the value that should appear in the branch instruction offset (lower half-word). In binary: 1111 1111 1111 1010 (two's complement). In hexadecimal: FFFA.

Checked with simulator and seems that my reasoning is correct since the instruction is coded as 0x1530FFFA.

Upvotes: 2

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