Routing tricks/ Changes that will allow design to route

Question

I've attempting to intergrate a encryption core into my design and have written a wrapper to do this.

I've come into issues however with routing:

Error: [fail_to_route]: Router fails. Shorts = 1430. Open nets = 0.

Are there any tricks that may help to route this design? I'm really inexperianced with HDL and I may have done soemthing silly which is causing this?

I do get another warning which could be something to do with it:

Warning: The following nets were assigned to global quadrant locations and contribute to high logic utilization within their quadrants: CLK_c (Location: UPPER_LEFT) Such high-utilization assignments can sometimes lead to increased routing congestion.

I think i'm correct in saying that enabling incremental routing/multiple passes can help this? but 1430 shorts is probably too many for this to help??

Any ideas/tips will be very much apreciated,

Regards, Mike

added: What are the most common pitfalls for newbies? I can't help but feel I may be suffering the results of one and the CORE usage of my design is only 53% and I cannot route.

Answer 1

I'm not familiar with your toolchain or device, but since you apparently have a clock signal contributing to high logic usage, could it be that it is routed as a normal logic signal, and not using a dedicated clock line?

You only have a limited number of clock lines (at least in the Xilinx devices I normally work with), so if you've used them all, the router might try to just use standard logic lines - although you should probably get at least a warning about this.

One way to get clock line usage down is to run everything on the same (fast) clock (if possible), and then use clock enables in the individual clocked processes to create slower running processes when necessary. In my early FPGA days I wasn't aware of this, and often created numerous derived clocks in logic - which is also a Bad Thing for other reasons than just clock line usage.

Answer 2

It would be helpful if you indicate the tools you are using and part you are targeting.

In general, successful routing is about successfully connecting all logical entities that must be connected to implement your design. PLDs, including FPGAs have limited number of physical resources to route your signals. When you run out of resources to route, routing fails.

Another point to consider is even if your design correctly routes, then it may still fail to meet your timing constraints. For example, you may need your design to run at 100MHz. But there are critical paths in your design that cannot run at that speed without violating setup and hold requirements of logic elements.

Bottom line is that failing to route is usually because you are out of target resources. You could be out of resources because of inefficient use of your target resources or because you are just trying to pack too much into the target that you have.