StackOverflow Questions for Tag: memory-segmentation

Grigory Rechistov
Grigory Rechistov

Reputation: 2224

x86 LDTR on 64-bit OSes: is it safe to assume that it is always zero?

Score: 1

Views: 34

Answers: 0

Read More
Joshua
Joshua

Reputation: 43327

jwasm -bin align BSS to 4

Score: 1

Views: 29

Answers: 0

Read More
user2804021
user2804021

Reputation: 161

What will be the output of this? Please explain it also

Score: -12

Views: 148

Answers: 2

Read More
osgx
osgx

Reputation: 94445

Is it possible a unix or linux for 80286 machine (or any machine without memory page mechanism)

Score: 6

Views: 3094

Answers: 6

Read More
OLC Yousra
OLC Yousra

Reputation: 11

Difference between effective and physical address

Score: 1

Views: 166

Answers: 3

Read More
distributed
distributed

Reputation: 175

Does x86 prefetch outside of code segment?

Score: 1

Views: 66

Answers: 1

Read More
SmRndGuy
SmRndGuy

Reputation: 1819

What would happen if the CS segment register is changed? (And how would you do so?)

Score: 10

Views: 6051

Answers: 2

Read More
tryingtobeastoic
tryingtobeastoic

Reputation: 195

How can the Intel 8086 access the entirety of the address space at a given time when using memory segmentation?

Score: 1

Views: 105

Answers: 1

Read More
Rajiv Kumar Srivastav
Rajiv Kumar Srivastav

Reputation: 111

GCC compiler option to get ES Segment Override prefix in x86?

Score: 0

Views: 1057

Answers: 2

Read More
Jonathan Garcia
Jonathan Garcia

Reputation: 33

How to Replace Unsafe with VarHandle or Foreign API

Score: 3

Views: 140

Answers: 2

Read More
Frink
Frink

Reputation: 21

How does an assembler find the offset of a label without knowing the value of the segment register?

Score: 1

Views: 82

Answers: 1

Read More
Michael Petch
Michael Petch

Reputation: 47603

Should using MOV instruction to set SS to 0x0000 cause fault #GP(0) in 64-bit mode?

Score: 10

Views: 1491

Answers: 1

Read More
user10744035
user10744035

Reputation:

Where is the Linear Address Space located?

Score: 1

Views: 1086

Answers: 3

Read More
wang fuqiang
wang fuqiang

Reputation: 61

when load control register during in switching real mode to protect mode

Score: 1

Views: 50

Answers: 0

Read More
QZero
QZero

Reputation: 43

How does CPU addressing the next instruction immediately after switching into protection mode?

Score: 3

Views: 89

Answers: 1

Read More
Wadosh
Wadosh

Reputation: 45

SIGSEGV on x86/x64 due to conflict between raw memory access and DS register in C compiled with TCC as JIT engine on Linux

Score: 1

Views: 126

Answers: 2

Read More
Changda Li
Changda Li

Reputation: 143

OS & Assembly: What prevents user mode from setting selector to arbitrary value?

Score: 3

Views: 1005

Answers: 2

Read More
Theodoros Mpalis
Theodoros Mpalis

Reputation: 21

Why does far call "call far ptr label" MASM syntax not work as intended?

Score: 0

Views: 186

Answers: 0

Read More
CarloC
CarloC

Reputation: 181

Wow64 subsystem and its implementation on x86_64

Score: 4

Views: 309

Answers: 1

Read More
IRP_HANDLER
IRP_HANDLER

Reputation: 308

x86 - Switching from 32-bit to 64-bit via RETF

Score: 3

Views: 393

Answers: 1

Read More
PreviousPage 1Next