CODEWITHSUNDEEP
binarylogicvhdl
redlogic
redlogic

Reputation: 1

16-bit numbers multiplication

In this code, I'm trying to multiplicate 16-bit numbers and get 32-bit output. Code has an error. At line

    c<=c+a;

compiler gives an error: "cant read port 'c' of mode out. What is my mistake? Thank you.

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;

    entity circ is
    port (  a    :in std_logic_vector (15 downto 0);
    b    :in std_logic_vector (15 downto 0);
    c    :out  std_logic_vector (31 downto 0)
        );

    end entity;

    architecture data of circ is
    begin
process(a,b)
begin
c<= '0';   
for i in 15 to 0 loop
if (b(i) = '1') then
c<=c+a;
end if;
END LOOP;

end process;
    end data;

Upvotes: 0

Views: 2560

Answers (1)

Paul S
Paul S

Reputation: 7755

The error is exactly what the compiler told you

cant read port 'c' of mode out

You can't read an output. You're reading c when you write c <= c + a because c appears on the right hand side of the assignment. You'd have to re-write the code like this:

signal s : std_logic_vector(31 downto 0);

process(a,b)
begin
  s <= (others => '0');   
  for i in 15 to 0 loop
    if (b(i) = '1') then
      s <= s + a; -- Use a local signal that we can read and write
    end if;
  end loop;
  c <= s; -- Assign the output to the local signal.
end process;

Upvotes: 1

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