CODEWITHSUNDEEP
verilogintel-fpga
user405725
user405725

Reputation:

How to get rid of a fitter warning about LVDS complement pin?

I have a clock input to the fan-out buffer which drives LVDS input to the bottom edge of PLL input. There are two pins - AJ19 (active high) and a complementary AK19 pin (active low). I am only interested in AJ19, so my top level module looks like this:

module top(clk, ...);
...
endmodule

Here is my pinout for a clk:

set_instance_assignment -name IO_STANDARD LVDS -to clk
set_location_assignment PIN_AJ19 -to clk
set_location_assignment PIN_AK19 -to "clk(n)"

So far so good, but fitter is generating a very annoying warning that drives me crazy:

Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Warning (176674): Following 1 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
    Warning (176118): Pin "clk" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk(n)"

Altera's knowledge base suggested to actually define the clock as a pair (i.e. input wire [1:0] clk) to remove the warning. That doesn't quite help because then you get another warning, saying that input pin does not drive any logic.

I have tried to disable this warning using // altera message_off 176118. That results in error because "176118" is not a valid message ID.

Any suggestions on how to solve this problem?

Upvotes: 1

Views: 3729

Answers (2)

shuckc
shuckc

Reputation: 2994

See Altera "Designing with Low-Level Primitives User Guide" for primitive details and templates http://www.altera.co.uk/literature/ug/ug_low_level.pdf

Example of wrapping top level block:

module top_wrap (
    ...
    input wire refclk,  input wire refclk_n,
  );

    // differential input buffers
  wire int_refclk;
  ALT_INBUF_DIFF inbuf_refclk (
    .i (refclk),
    .ibar (refclk_n),
    .o(int_refclk),
  );

  top wrapped (
      .refclk( int_refclk),
      ...
  )
endmodule

Upvotes: 2

Martin Thompson
Martin Thompson

Reputation: 16812

To get rid of this, you need to create both signals, and then take them into an LVDS buffer component (I don't recall what Altera calls this component off the top of my head), the output of which will drive a "normal" internal signal that you can then use as you see fit.

Upvotes: 2

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