CODEWITHSUNDEEP
syntaxvhdl
Laserbeak43
Laserbeak43

Reputation: 609

VHDL - Interfacing with specific ports on a bus

I have a bus: 

    A(7 downto 0)

and i'm creating an component that interfaces with it on 7, 6 and 0, is there a way for me to create a 

    std_logic_vector(7,6,0)?

simply for the sake of staying consistent with the pins on bus A()? I'm sure i could do something like:

    std_logic_vector(2 downto 0) -- or maybe even
    ASeven, Asix, Azero : in std_logic;

and assign the pins accordingly, but it'd be a lot nicer for reference etc(i think) if i could create a vector.

Thanks in Advance! :)

Upvotes: 1

Views: 962

Answers (1)

BennyBarns
BennyBarns

Reputation: 620

You can't. Either make a signal x(7 downto 0) and disregard the spare signals (the compiler/synthesizer will do, anyway), or you can use an appropriate assignment in your port map like
port map(
myoutport(0) => aZero,
...
 or something. In general, use the first variant, as it is more consistent.

Upvotes: 2

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