CODEWITHSUNDEEP
vhdl
bltpyro
bltpyro

Reputation: 320

Generate ports in VHDL?

Is there a way to generate port declarations in VHDL? I would like to do something similar to #IFDEF for debug signals out to pins for an oscope. That way I can quickly enable or disable debug logic. For example:

entity my_entity is
port (  

    debug_label: if debug_on = 1 generate
    debug1: out;
    end debug_label;

    ....

    );
end component;

When I try something like this is doesn't work. Is there any way to make it work? Or an alternative way to do something similar?

Upvotes: 3

Views: 5613

Answers (1)

Morten Zilmer
Morten Zilmer

Reputation: 15924

The ports can't be conditional, but the length of for example a std_logic_vector can be configurable through a generic, and the length may even be 0, resulting in null range. An entity showing this is:

entity mdl is
  generic(
    DEBUG_LEN : natural := 0);
  port(
    ...
    debug_o : out std_logic_vector(DEBUG_LEN - 1 downto 0));
end entity;

You should run a test synthesis to see how the your selected synthesis tool handles null range when assigning to pins.

Upvotes: 3

Related Questions