CODEWITHSUNDEEP
vhdl
refDL
refDL

Reputation: 89

Optional PORTs in VHDL?

I am writing an IP-Core and depending on which generic parameters user chooses not all OUT/IN Ports are needed. Is it possible to have optional Ports? I know something similar should be possible, since when I use Xilinx IP-Cores, depending on parameters not all PORTs are included.

Upvotes: 3

Views: 3610

Answers (1)

Morten Zilmer
Morten Zilmer

Reputation: 15924

Ports can't be optional, but usage of ports can be, which for the designer is as if they are not there.

Input ports that are not mapped (used) must have a default value in the entity, and output ports can simply be left unmapped.

If an entity is declared like for example:

entity mdl_sub is
  generic(
    A_C_USE : boolean := FALSE;
    B_D_USE : boolean := FALSE);
  port(
    clk_i : in  std_logic;
    rst_i : in  std_logic;
    a_i   : in  std_logic := 'X';
    b_i   : in  std_logic := 'X';
    c_o   : out std_logic;
    d_o   : out std_logic);
end entity;

Then the module can be used in the different configuration like below, where the use of ports can then differ based on the configuration:

-- Using port a_i and c_o
mdl_sub_0 : entity work.mdl_sub
  generic map(
    A_C_USE => TRUE)
  port map(
    clk_i => clk_i,
    rst_i => rst_i,
    a_i   => m0_a_i,
    c_o   => m0_c_o);

-- Using port b_i and d_o
mdl_sub_1 : entity work.mdl_sub
  generic map(
    B_D_USE => TRUE)
  port map(
    clk_i => clk_i,
    rst_i => rst_i,
    b_i   => m1_b_i,
    d_o   => m1_d_o);

All signals and ports are std_logic.

Upvotes: 7

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