VHDL Entitry Port Does Not Match With Type Of Component Port

Question

My project looks something like the following: Block Diagram and when I run a simulation with a generated test bench, the following error comes up: [VRFC 10-3290] entity port 'ina_0' does not match with type signed of component port ["C:/Users/sendm/AppData/Roaming/Xilinx/Vivado/test_design_1.vhd":12] Which is weird since all of my type declarations match, using the same library and type (relevant code below)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity test_design_1 is 
end test_design_1;

architecture TB of test_design_1 is

component design_1 is
port (
  InA_0 : in signed (3 downto 0);
  InB_0 : in signed (3 downto 0);
  InBits_0 : in STD_LOGIC_VECTOR (2 downto 0);
  Output_0 : out signed (7 downto 0)
);
end component design_1;

signal InA_0 : signed (3 downto 0);
signal InB_0 : signed (3 downto 0);
signal InBits_0 : STD_LOGIC_VECTOR (2 downto 0);
signal Output_0 : signed (7 downto 0);
begin

DUT: component design_1 port map (
  InA_0 => InA_0,
  InB_0 => InB_0,
  InBits_0 => InBits_0,
  Output_0 => Output_0
);

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity Selection is
Port 
( 
InBits:in std_logic_vector(2 downto 0); --input bits for selection
OutToAdder:out std_logic; --output to adder block, 1 for addition 0 for subtraction
ClockToAdder:out std_logic; --output to enable adder block, 1 for on 0 for off
OutToMultiplier:out std_logic; --output enable multiplier block, 1 for on 0 for off
  
InA: in signed (3 downto 0); --for sharing inputs
InB: in signed (3 downto 0);
OutA: out signed (3 downto 0);
OutB: out signed (3 downto 0)
);
end Selection;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity SharedOutPut is
Port 
( 
    AddIn:In Signed (3 downto 0); --input from the adder
    MultiIn: In Signed (7 downto 0); --input from the multiplier
    
    AddEnable:in std_logic; --indicates which input is going to be mapped to the output
    MultiEnable:in std_logic;
    
    Output: Out Signed (7 downto 0)
);
end SharedOutPut;

The design_1 Generated by Xilinx is below, the file is read-only so I'm not sure if I should touch it.

--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.1.1 (win64) Build 2960000 Wed Aug  5 22:57:20 MDT 2020
--Date        : Sun Feb 28 13:18:33 2021
--Host        : MSI running 64-bit major release  (build 9200)
--Command     : generate_target design_1.bd
--Design      : design_1
--Purpose     : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1 is
  port (
    InA_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    InB_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    InBits_0 : in STD_LOGIC_VECTOR ( 2 downto 0 );
    Output_0 : out STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute CORE_GENERATION_INFO : string;
  attribute CORE_GENERATION_INFO of design_1 : entity is "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=4,numReposBlks=4,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
  attribute HW_HANDOFF : string;
  attribute HW_HANDOFF of design_1 : entity is "design_1.hwdef";
end design_1;

architecture STRUCTURE of design_1 is
  component design_1_c_addsub_0_0 is
  port (
    A : in STD_LOGIC_VECTOR ( 3 downto 0 );
    B : in STD_LOGIC_VECTOR ( 3 downto 0 );
    CLK : in STD_LOGIC;
    ADD : in STD_LOGIC;
    S : out STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  end component design_1_c_addsub_0_0;
  component design_1_mult_gen_0_0 is
  port (
    CLK : in STD_LOGIC;
    A : in STD_LOGIC_VECTOR ( 3 downto 0 );
    B : in STD_LOGIC_VECTOR ( 3 downto 0 );
    P : out STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  end component design_1_mult_gen_0_0;
  component design_1_SharedOutPut_0_0 is
  port (
    AddIn : in STD_LOGIC_VECTOR ( 3 downto 0 );
    MultiIn : in STD_LOGIC_VECTOR ( 7 downto 0 );
    AddEnable : in STD_LOGIC;
    MultiEnable : in STD_LOGIC;
    Output : out STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  end component design_1_SharedOutPut_0_0;
  component design_1_Selection_0_8 is
  port (
    InBits : in STD_LOGIC_VECTOR ( 2 downto 0 );
    OutToAdder : out STD_LOGIC;
    ClockToAdder : out STD_LOGIC;
    OutToMultiplier : out STD_LOGIC;
    InA : in STD_LOGIC_VECTOR ( 3 downto 0 );
    InB : in STD_LOGIC_VECTOR ( 3 downto 0 );
    OutA : out STD_LOGIC_VECTOR ( 3 downto 0 );
    OutB : out STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  end component design_1_Selection_0_8;
  signal InA_0_1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal InB_0_1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal InBits_0_1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal Selection_0_ClockToAdder : STD_LOGIC;
  signal Selection_0_OutA : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal Selection_0_OutB : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal Selection_0_OutToAdder : STD_LOGIC;
  signal Selection_0_OutToMultiplier : STD_LOGIC;
  signal SharedOutPut_0_Output : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal c_addsub_0_S : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal mult_gen_0_P : STD_LOGIC_VECTOR ( 7 downto 0 );
begin
  InA_0_1(3 downto 0) <= InA_0(3 downto 0);
  InB_0_1(3 downto 0) <= InB_0(3 downto 0);
  InBits_0_1(2 downto 0) <= InBits_0(2 downto 0);
  Output_0(7 downto 0) <= SharedOutPut_0_Output(7 downto 0);
Selection_0: component design_1_Selection_0_8
     port map (
      ClockToAdder => Selection_0_ClockToAdder,
      InA(3 downto 0) => InA_0_1(3 downto 0),
      InB(3 downto 0) => InB_0_1(3 downto 0),
      InBits(2 downto 0) => InBits_0_1(2 downto 0),
      OutA(3 downto 0) => Selection_0_OutA(3 downto 0),
      OutB(3 downto 0) => Selection_0_OutB(3 downto 0),
      OutToAdder => Selection_0_OutToAdder,
      OutToMultiplier => Selection_0_OutToMultiplier
    );
SharedOutPut_0: component design_1_SharedOutPut_0_0
     port map (
      AddEnable => Selection_0_ClockToAdder,
      AddIn(3 downto 0) => c_addsub_0_S(3 downto 0),
      MultiEnable => Selection_0_OutToMultiplier,
      MultiIn(7 downto 0) => mult_gen_0_P(7 downto 0),
      Output(7 downto 0) => SharedOutPut_0_Output(7 downto 0)
    );
c_addsub_0: component design_1_c_addsub_0_0
     port map (
      A(3 downto 0) => Selection_0_OutA(3 downto 0),
      ADD => Selection_0_OutToAdder,
      B(3 downto 0) => Selection_0_OutB(3 downto 0),
      CLK => Selection_0_ClockToAdder,
      S(3 downto 0) => c_addsub_0_S(3 downto 0)
    );
mult_gen_0: component design_1_mult_gen_0_0
     port map (
      A(3 downto 0) => Selection_0_OutA(3 downto 0),
      B(3 downto 0) => Selection_0_OutB(3 downto 0),
      CLK => Selection_0_OutToMultiplier,
      P(7 downto 0) => mult_gen_0_P(7 downto 0)
    );
end STRUCTURE;

Any insights on the above matter will be appriciated

Answer 1

The problem is that you are trying to write decent VHDL, but using the Xilinx-provided automatic test bench generator.

This, for reasons for its own, and quite unnecessarily, translates all port types and testbench signals into std_logic and std_logic_vector, which are incompatible with the object it is attempting to test.

If you aren't planning on doing gate-level simulations (post-synth and/or post-PAR) just edit the port types in the auto-generated testbench to signed, as they should be. There is no harm in doing this, all the tool has done is provide a very crude (and wrong!) starting point for your actual testbench.

(Later, if you need to run post-PAR simulations which I never normally do, unless I'm chasing a suspected synthesis tool bug, you'll run into the opposite problem. The post-synthesis netlist will have translated all your ports into std_logic and std_logic_vector, which are no longer compatible with the modified testbench. This can best be solved by creating a wrapper entity with the correct port types, and instantiating the netlist inside it.)