CODEWITHSUNDEEP
verilogmodelsim
Slater Victoroff
Slater Victoroff

Reputation: 21934

zero flag in verilog problems

I am attempting to build a 32 bit ALU in verilog and I've only done a small bit of behavioral verilog before, so I'm having some difficulty with this code: 

module ZERO_FLAG(flag, control, inputA, inputB);
  input [2:0] control;
  input [31:0] inputA, inputB;
  output flag;

  reg flag;

  always @(control or inputA or inputB) begin
    case (control)
      1: flag <= (|(inputA ~& inputB));
      3'bxxx, 3'bxx0, 3'bxx1, 3'bx0x,
      3'bx00, 3'bx01, 3'bx1x, 3'bx10,
      3'bx11, 3'b0xx, 3'b0x0, 3'b0x1,
      3'b00x, 3'b000, 3'b01x, 3'b010,
      3'b011, 3'b1xx, 3'b1x0, 3'b1x1,
      3'b10x, 3'b100, 3'b101, 3'b11x,
      3'b110, 3'b111: flag <= 0;
    endcase
  end
endmodule

For some reason Modelsim is simply unhappy with the NAND between inputA and inputB in the case of 1. The basic idea is that I only want to throw a zero flag when subtraction is happening, and then I want the result to be an OR reduced bitwise NAND of the two inputs. Thoughts?

Upvotes: 0

Views: 2721

Answers (3)

Morgan
Morgan

Reputation: 20554

It is worth mentioning to complement the other answers that under IEEE 1364.1-2002 A.8.6 That ~& is valid Verilog syntax but available only as a unary operator. This means that it will only take a right hand argument.

 &(4'b0000) => 1'b0
 &(4'b0101) => 1'b0
 &(4'b1111) => 1'b1

~&(4'b0000) => 1'b1
~&(4'b0101) => 1'b1
~&(4'b1111) => 1'b0

The available unary operators are:

+, -, !, ~, &, ~&, |, ~|, ^, ~^, ^~

Of these &, ~&, |, ~|, ^, ~^, ^~ are reduction operators, as shown above will reduce down to 1 bit values. The ^ implies XOR.

The available bitwise operators :

+, -, *, /, %, ==, !=, ===, !==, &&, ||, **,
<, <=, >, >=, &, |, ^, ^~, ~^, >>, <<, >>>, <<<

Upvotes: 2

user597225
user597225

Reputation:

Unfortunately there is no binary NAND in Verilog. The only binary bitwise operators are AND(&), OR(|), XOR(^) and XNOR(both ~^ and ^~).

Upvotes: 0

B Pete
B Pete

Reputation: 946

I would try rewriting the line as:

1: flag <= |(~(inputA & inputB));

Upvotes: 2

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