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Andry
Andry

Reputation: 16845

How to represent array literals in VHDL?

I have the following type declarations:

type cachesubset is record
                      tag     : std_logic_vector(3 downto 0);
                      word0   : w32;
                      word1   : w32;
                      dirty   : std_logic;
                      valid   : std_logic;
                    end record;

type    cacheset is record
                      lru : std_logic;
                      subsets: array(0 to 1) of cachesubset
                    end record;

I want to define the empty cacheset constant:

constant 
empty_cachesubset : cachesubset := (
                                    tag   => "0000",
                                    word0 => "00000000000000000000000000000000",
                                    word1 => "00000000000000000000000000000000",
                                    dirty => '0',
                                    valid => '0'
                                   );

constant 
empty_cacheset    : cacheset    := (
                                    lru     => '0',
                                    subsets => ???
                                   );

The point is that I do not know how to create an array literal.

Some notes...

Please, do not mind the fact that I am using two separate fields to address words in a subset while I might do the same for a cacheset and the subsets... the point is that I will also apply an array for words in a subset...

Upvotes: 2

Views: 646

Answers (2)

user1818839
user1818839

Reputation: 

subsets => ???

The simplest way is to set every entry in the array to the same value...

subsets => (others => empty_cachesubset);

As the other answer shows, you can set individual elements to different values - then use "others" to default the rest.

Upvotes: 0

Hendrik
Hendrik

Reputation: 1247

You can do this like this:

library ieee;
use ieee.std_logic_1164.all;

package test is
    subtype w32 is std_logic_vector(31 downto 0);

    type cachesubset is record
        tag   : std_logic_vector(3 downto 0);
        word0 : w32;
        word1 : w32;
        dirty : std_logic;
        valid : std_logic;
    end record;

    type subsetst is array (0 to 1) of cachesubset;

    type cacheset is record
        lru     : std_logic;
        subsets : subsetst;
    end record;

    constant empty_cachesubset : cachesubset := (
        tag => (others => '0'),
        word0 => (others => '0'),
        word1 => (others => '0'),
        dirty => '0',
        valid => '0'
    );

    constant empty_cacheset : cacheset := (
        lru         => '0',
        subsets     => (
            0 => empty_cachesubset,
            1 => (
                tag => (others => '0'),
                word0 => (others => '0'),
                word1 => (others => '0'),
                dirty => '0',
                valid => '0'
            )
        )
    );
end package test;

Upvotes: 2

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