CODEWITHSUNDEEP
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orpqK
orpqK

Reputation: 2795

How to determine the number of Logic cells and MLUTS

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So from looking at this diagram, I am trying to figure out how these answers came to be? Could someone explain to me?

A) Register R0 to R2 require 32 logic cells total, each cell implement a 3 stage shift reg using 1 MLUT operating in Shift Reg. mode.

B) R3 require 32 logic cells each implement a RC adder, using 1 carry and 1 MLUT in ROM mode.

C) the subtractor and adder each require 16 logic cells using 1 MLUT in ROM mode

D) the comparator need 16 logic cell and 1 MLUT in ROM mode.

Upvotes: 0

Views: 2188

Answers (2)

ice
ice

Reputation: 127

I assume that you're working on the Xilinx FPGA and I'm not sure why you are only getting 1 MLUT for each component but I'll try to explain.

An easy way to understand this is to understand that a logic cell contains a single lookup table (LUT), and MLUT is simply a LUT with memory capability. Each LUT is capable of outputting 1-bit for a set of 6-input (for the later Xilinx FPGA families). As such, for every 1-bit output, you'll need one LUT.

B) R3 require 32 logic cells each implement a RC adder, using 1 carry and 1 MLUT in ROM mode.

C) the subtractor and adder each require 16 logic cells using 1 MLUT in ROM mode

easily fall in the described category.

Now, let us look at the special cases:

A) Register R0 to R2 require 32 logic cells total, each cell implement a 3 stage shift reg using 1 MLUT operating in Shift Reg. mode.

consumes 32 logic cells because it utilizes a special mode of operation within a Xilinx MLUT, which is a shift register.

D) the comparator need 16 logic cell and 1 MLUT in ROM mode.

The comparator requires 16 logic cells because each stage's result is depended on the previous stage, much like an adder. Therefore, you'll need 16 of them to compare the result properly.

It must be noted that the above description only apply to Xilinx FPGAs and not FPGAs from other companies. FPGAs from other companies have different design approach and cannot be directly translated or compared.

I'd suggest you to read up on the Xilinx's resource website on how LUT and CLB are constructed. This should give you better understanding.

Hope this helps.

Upvotes: 1

user2099996
user2099996

Reputation: 134

What is an MLUT? It depends on your FPGA architecture. Just use the synthesis tool from your vendor to get the numbers for your device.

Upvotes: 0

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