CODEWITHSUNDEEP
vhdl
ted
ted

Reputation: 4985

When to use what types

Questions:

  1. Is there a more appropiate "supertype" to signed and unsigned than std_logic_vector (regarding my case)?

  2. Is it ok to define an Input as (subtype of) Integer or is it better to define it as bitvector? (Are there any Issues with the Integer approach)

  3. When should I use resolved or unresolved logic for the Inputs/Outputs off an Entity?

    • Resolved for Bus drivers (because of the "high Z drivers") otherwise unresolved?
    • Always resolved so a bus can be driven/used as input (this seems wrong, because when would I use unresolved then?)

Actual Case:

I am declaring an entity and am wondering for the right types for the inputs and outputs. Lets assume I am constructing a dynamic width equal. It compares the first n Bits of two Inputs for equality.

The entity definition would be:

entity comparisonDynWidth is
    generic(
        width       : positive;
        min_width   : positive;
            -- when the tools suport vhdl2008 enough
            -- reason for both signed/unsigned => std_logic inputs
        --function compareFunc (x: in std_logic_vector; y: in std_logic_vector)  return std_logic 
    );
    port (
        left, right : in  std_logic_vector(width-1 downto 0);
        widthControl: in  natural range 0 to width-min_width;
        result      : out std_logic / std_ulogic ??
    );

I chose std_logic_vector as Input since I want it to look the ports like a generic less than comparator as well, for which signedness matters and which can have signed and unsigned inputs. since it is easier for me to define the width as an integer I did so.

Upvotes: 0

Views: 965

Answers (2)

Martin Thompson
Martin Thompson

Reputation: 16822

Is there a more appropiate "supertype" to signed and unsigned than std_logic_vector (regarding my case)?

Not sure what you mean, but you have no choice - signed and unsigned are defined in the standard.

Is it ok to define an Input as (subtype of) Integer or is it better to define it as bitvector? (Are there any Issues with the Integer approach)

Integers will flag errors if you go outside their range. vectors (signed and unsigned) will wrap around. Which is "correct" depends on what you want and how you feel about coding explicit wrap-around if you want it with integers.

When should I use resolved or unresolved logic for the Inputs/Outputs off an Entity?

If you stick to:

  • only using resolved types for the top level IO ports (i.e. the actual pins of the device)
  • using unresolved types internally

you will be able catch errors involving multiple drivers on a signal with a detailed error-message at elaboration-time. This can be preferable to chasing down Xs in your waveforms at simulation-time.

There are no internal tri-state buses internally to most technologies these days, so you can't have multiple drivers, so there's no need for resolved signals inside the device. IO pins (almost?) always have tri-stateble drivers, so the use of a resolved type is appropriate, and the driving of a 'Z' can be used to infer that behaviour.

Upvotes: 1

baldyHDL
baldyHDL

Reputation: 1387

  1. std_logic_vector is a good choice in your case (and in most cases in an entity, as it represents hardware situation best... e.g. with use of 'U' and 'Z' and so on)

  2. the use of integer in an entity is ok as long as it is not the top-level entity. in top level entities, the exclusive use of std_logic(_vector) is recommended.

  3. most tools report multi-driver situations anyway... the use of resolved types is therefore ok.

Upvotes: 1

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