CODEWITHSUNDEEP
vhdl
ferdepe
ferdepe

Reputation: 540

When do you use a block statement in a VHDL design and when do you not?

I come from SW world and recently I've started to create FPGA designs in VHDL. I've read about the block concurrent statement and its principal uses like organize architecture grouping concurrent code and guard signals, which is not recommendable.

But this is one of many possibilities in order to implement the same functionality. For instance, I've been implemented a CRC frame checker with a VHDL function. It has one bit value input, and return a register with the cumulative CRC value of all bit inputs.

I think the same functionality can be implemented with a block. What is the best option for resource utilization? When would you use a block and when would not? Which is the best case to implement a block?

Thanks,

Upvotes: 3

Views: 4226

Answers (1)

ice
ice

Reputation: 127

What is the best option for resource utilization?

There should be no different between with or without block in terms of resource utilization. This assumes that you're creating the same logic.

When would you use a block and when would not?

Similar to software, the only reason you want to use block statement is when you want to limit the scope of the variables used within a portion of the code. This can significantly improve code readability in a large design where signals can be declared and utilized in the same region.

I would not recommend anyone to use block statement in a small design, or where component instantiation is more appropriate.

Which is the best case to implement a block?

When it improves code readability.

Upvotes: 3

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