CODEWITHSUNDEEP
vhdl
titan
titan

Reputation: 53

VHDL Syntax explanation needed

Can somebody explain what the following line of code does? Google search did not turn up anything useful.

data_count <= (others => ’0’);

Thanks!

Upvotes: 3

Views: 134

Answers (2)

abkds
abkds

Reputation: 1794

This statement sets all the elements to'0' You can also use this statement as others => '1' this will set elements to '1'

suppose data_count is a std_logic_vector( 6 downto 0 ) , then the data_ count will be assigned as data_count <= "0000000"

suppose you write data_count <= (5 => '1' , others => ’0’);

and data_count suppose is a std_logic_vector( 7 downto 0 ) , this means 6th bit is 1 and rest are 0 ie

data_count <= "00100000" ;

Upvotes: 2

Philippe
Philippe

Reputation: 3730

It sets all elements of data_count to '0'.

The datatype of data_count would be an array of elements that can be '0', like bit_vector, std_logic_vector, signed or unsigned. If your signal data_count has four bits, this would be equivalent to writing:

data_count <= "0000";

with the advantage that you don't have to count the bits.

You can also set certain elements to '1' and then the rest to '0': 

data_count <= (1 => '1', 3 => '1', others=>'0');

Upvotes: 4

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