CODEWITHSUNDEEP
syntaxconcatenationvhdl
hops1
hops1

Reputation: 23

VHDL, confused over syntax "" &

There's some VHDL code I'm going through for finals and came across some confusing syntax. I understand that it is because of type differences but don't really understand what's going on. I'll only post the relevant part of the code and the libraries used

USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

count : IN std_logic;
SIGNAL qi : unsigned(w downto 0);

qi <= qi + ("" & count);

Basically my question is, what's ' "" & ' , does the concatenation with "" do an automatic conversion to the other type?

Thanks in advance

EDIT

Cause of the type conversion confusion here's the rest of the code

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY counter_alt IS
GENERIC (w : integer := 8);
PORT (clk, load, count : IN std_logic;
        d : IN unsigned(w-1 downto 0);
        q : OUT unsigned(w-1 downto 0);
        co : OUT std_logic);
END counter_alt;


ARCHITECTURE bhv OF counter_alt IS
SIGNAL qi : unsigned(w downto 0);

BEGIN
    PROCESS(clk)
        BEGIN
        IF rising_edge(clk) THEN

        IF load='1' THEN 
        qi <= '0' & d;
        ELSE qi <= qi + ("" & count);
        END IF;
        END IF; 

    END PROCESS;
q <= qi(w-1 downto 0);
co <= qi(w); 
END bhv;

Upvotes: 1

Views: 4890

Answers (3)

Jim Lewis
Jim Lewis

Reputation: 3973

"" simply designates a null string literal. By concatenating it with std_logic, it becomes some array type based on std_logic. Since the "+" operator for adding with an unsigned only supports an unsigned or natural typed value (pre-vhdl-2008), the string value is resolved to unsigned.

The same sort of type resolution happens when you add with a string literal value:

qi <= qi + "0101" ;

With VHDL-2008, you can now add an unsigned with a std_ulogic (and as a result also std_logic):

qi <= qi + count;

Upvotes: 0

Morten Zilmer
Morten Zilmer

Reputation: 15924

The empty string "" is an empty unsigned vectors in that context, since the USE ieee.numeric_std.ALL; is included, and the relevant expression involves signals of type unsigned.

So the result of ("" & count) has type unsigned, thus can be used in addition without any further type conversion. The concat with "" serves as an implicit type conversion to unsigned in that case.

Upvotes: 1

andrsmllr
andrsmllr

Reputation: 1223

By concatenating an empty string "" to a std_logic value a std_logic_vector is returned. This can be useful if a std_logic value shall be used in an arithmetic expression. The resulting std_logic_vector can then be cast to the desired type, e.g. signed(quite useless for a number which is 1 bit wide), unsigned, integer...
Thus, in your example a type cast should still be required, since VHDL does no automatic type conversion from std_logic_vector to unsigned.

Upvotes: 1

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