CODEWITHSUNDEEP
vhdl
weider
weider

Reputation: 103

VHDL, how does concatenate work?

I have some code in VHDL. I don't understand how concatenation works.

A   : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B   : IN IN STD_LOGIC;
A <= "1111";
B <= '0';


A <= A(2 DOWNTO 0) & B;

Is A "0111" or "1110"?

Upvotes: 2

Views: 7283

Answers (1)

Casperrw
Casperrw

Reputation: 531

As far as the concatenation itself is concerned, you seem to be doing that right, but apart from the other errors (you're assigning to an input, as BrianDrummond noted, and you've not got compilable syntax), you'll have a problem because VHDL signal assignments outside of a process are concurrent (i.e. they are evaluated continuously and in parallel).

So if you do:

A <= "1111";
A <= A(2 DOWNTO 0) & B;

You'll be assigning every bit of A with two drivers - a '1', and the bit on the left of it except for the least significant bit which gets assigned 'B'. Imagine constructing this with actual copper wires. You are tying all bits of A together - AND tying them to the positive voltage source. If B is '1' this should resolve to all '1', but if B is '0' you will effectively connect the positive and negative voltage terminals, like a short circuit. Your simulator will tell you the result is 'X' - unknown.

Upvotes: 2

Related Questions