CODEWITHSUNDEEP
verilog
harrym
harrym

Reputation: 121

IF with ternary operator - Verilog

I am trying to write a program in Verilog that should "move" a light LED on an array of LEDs. With a button the light should move to the left, with another one it should move to the right. This is my code:

module led_shift(UP, DOWN, RES, CLK, LED);
input UP, DOWN, RES, CLK;
output reg [7:0] LED;
reg [7:0] STATE;

always@(negedge DOWN or negedge UP or negedge RES)
begin
    if(!RES)
    begin
        STATE <= 8'b00010000;
    end
    else
    begin
        STATE <= UP ? STATE>>1 : STATE<<1;
    end
end

always @ (posedge CLK)
begin
    LED <= STATE;
end
endmodule

The problem is in STATE <= UP ? STATE>>1 : STATE<<1; and the error the following:

Error (10200): Verilog HDL Conditional Statement error at led_shift.v(34): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct

I tried to modify the code without using that kind of if:

always@(negedge DOWN or negedge UP or negedge RES)
begin
    if(!RES)
        STATE <= 8'b00010000;
    else
    begin   
        if(!DOWN)
            STATE <= STATE<<1;
        else
        begin
            if(!UP)
                STATE <= STATE>>1;
            else
                STATE <= STATE;
        end
    end
end

It compiles, but does not work: the LED "moves" only to the left, when I press the other button all LEDs shut down. Probably there is a problem in my code, but I cannot understand why my first code does not compile at all. Thank you for any help!

harrym

Upvotes: 1

Views: 2187

Answers (1)

Greg
Greg

Reputation: 19112

It is not clear for the synthesizer to know how to control STATE with the 3 asynchronous control signals.

Most likely your your synthesizer is trying to map STATE to a D flip flop with asynchronous active low set and reset. For example it might be trying to synthesize to something like:

dff state_0_(.Q(STATE[0], .CLK(DOWN), .SET_N(UP), .RST_N(RES(, .D(/*...*/));

In a real flop with asynchronous set and reset, the default should be consent and would explain the error in your first code. In your second attempt, UP becomes part of the combination logic cloud along with DOWN. DOWN is also being used as a clock. Since UP is not a clock, shifting continuously happens while UP is low, completely shifting the on bit out instantly. Another error for the second case would actually be more appropriate.

For the synthesizer to do a better job, you first need to synchronize your asynchronous control signals. Use the same technique as CDC (clock domain crossing; A paper by Cliff Cummings goes into detains here). A basic example:

always @(posedge clk) begin
    pre_sync_DOWN <= DOWN;
    sync_DOWN <= pre_sync_DOWN;
end

Now that the controls signals are synchronized, make STATE the output of your combination logic. Example:

always @* begin
    if(!sync_RES)
        STATE = 8'b00010000;
    else
      case({sync_UP,sync_DOWN})
        2'b01  : STATE = LED>>1;
        2'b10  : STATE = LED<<1;
        default: STATE = LED;
      endcase
end

With everything running on one clock domain and explicitly defined combination logic, the synthesizer can construct equivalent logic using flops and basic gates.

FYI:

To shift only on a negedge event you need to keep the last sync value and check for the high to low transition. Remember to swap sync_ with do_ in the combination logic that drives STATE.

always @(posedge clk)
    keep_DOWN <= sync_DOWN;
always @*
    do_DOWN = (keep_DOWN && !sync_DOWN);

Upvotes: 2

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