CODEWITHSUNDEEP
mipsvhdl
Iuli Sirbu
Iuli Sirbu

Reputation: 11

Shift left logical and shift right logical on MIPS

Can anyone tell if this is the correct code for shift left logical (sll) and shift right logical (srl) on MIPS?

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
-- library UNISIM;
-- use UNISIM.VComponents.all;

entity ALU is
  port (RdData1 : in  std_logic_vector (31 downto 0);
        RdData2 : in  std_logic_vector (31 downto 0);
        FAddr   : in  std_logic_vector (15 downto 0);
        ALUSrc  : in  std_logic;
        ALUOP   : in  std_logic_vector (2 downto 0);  --S-a marit lungimea lui ALUOP
        Y       : out std_logic_vector (31 downto 0));
end ALU;

architecture Behavioral of ALU is

  signal SEAddr : std_logic_vector(31 downto 0);
  signal OP2    : std_logic_vector(31 downto 0);

begin

  SEAddr(15 downto 0)  <= FAddr(15 downto 0);
  SEAddr(31 downto 16) <= x"0000" when FAddr(15) = '0' else x"FFFF";

  OP2 <= RdData2 when ALUSrc = '0' else SEAddr;

  with ALUOP select
    Y <= RdData1 + OP2 when "000",               --S-a marit lungimea lui ALUOP
         RdData1 - OP2              when "001",  --S-a marit lungimea lui ALUOP
         RdData1 and OP2            when "010",  --S-a marit lungimea lui ALUOP
         RdData1 or OP2             when "011",  --S-a marit lungimea lui ALUOP
         RdData1(30 downto 0) & "0" when "100",  --sll ,
         "0" & RdData1(1 downto 31) when "101",  --srl ,
         RdData1                    when others;

end Behavioral;

I'm adding the controler maybe my misstake is here, i will add a printscreen with my test banch wave for you to understand better why this is not working :

entity ctrl is
Port ( OP : in  STD_LOGIC_VECTOR (5 downto 0);
       Funct : in  STD_LOGIC_VECTOR (5 downto 0);
       ALUSrc : out  STD_LOGIC;
       ALUOP : out  STD_LOGIC_VECTOR (2 downto 0);--S-a marit lungimea lui ALUOP 
       MemWr : out  STD_LOGIC;
       Mem2Reg : out  STD_LOGIC;
       RegWr : out  STD_LOGIC;
       RegDest : out  STD_LOGIC);
end ctrl;

architecture Behavioral of ctrl is
signal OPCIntrn :   std_logic_vector(6 downto 0);
signal temp         :   std_logic_vector(7 downto 0); 

begin
with OP select
OPCIntrn (6) <= '0' when "000000",
    '1' when others;

with OP select
OPCIntrn (5 downto 0) <= Funct when "000000",
OP when others;

with OPCIntrn select
temp <=         b"0_000_0_0_1_1" when b"010_0000",  --add
        b"0_001_0_0_1_1" when b"010_0010",   --sub
        b"0_010_0_0_1_1" when b"010_0100",   --and
        b"0_011_0_0_1_1" when b"010_0101",   --or
        b"1_000_0_1_1_0" when b"110_0011",   --lw
        b"0_100_0_0_1_1" when b"000_0000",   --sll
        b"0_101_0_0_1_1" when b"000_0010",   --sll
        b"1_000_1_0_0_0" when b"110_1011",   --sw
        b"0_000_0_0_0_0" when others;


RegDest <= temp(0);
RegWr <= temp(1);
Mem2Reg <= temp(2);
MemWr <= temp(3);
ALUOP (2 downto 0) <= temp(6 downto 4);  
ALUSrc <= temp(7);


end Behavioral;

Upvotes: 1

Views: 2580

Answers (1)

Morten Zilmer
Morten Zilmer

Reputation: 15924

In the code above RdData1 is declared as std_logic_vector(31 downto 0) but for SRL the RdData1 is used as RdData1(1 downto 31). This creates a null range, which should result in tool warning.

This must be corrected to RdData1(31 downto 1).

The instruction definition for SLL and SRL can be seen here MIPS architecture.

Upvotes: 2

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