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mahmood
mahmood

Reputation: 24715

VHDL arithmetic shift_left

With the shift_left function of ieee.numeric_std, I want to shift a signal to left and insert 1 or 0 from the right.

signal qo: signed (3 downto 0) := (others=>'0');
qo <= shift_left(qo,1);

That will only insert 0 from right. I want to insert 1 upon some conditions.

Upvotes: 6

Views: 10606

Answers (2)

mkrieger1
mkrieger1

Reputation: 23189

Inserting '1' at the rightmost position of a signal of type signed means incrementing its value by 1. Likewise, not inserting '1' means incrementing its value by 0.

This is best expressed by the + operator which is overloaded by the numeric_std package:

-- Id: A.8
function "+" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Adds a SIGNED vector, L, to an INTEGER, R.

So simply use:

shift_left(qo, 1) + 1

respectively

shift_left(qo, 1) + 0

This works irrespective of how qo is defined, so if you later change the length of qo you don't need to adjust any slicing operations.

Upvotes: 1

Matthew
Matthew

Reputation: 13977

Instead of using the shift_left function, how about using slicing and concatenation:

qo <= qo(2 downto 0) & '1';

or

qo <= qo(2 downto 0) & '0';

Personally, I recommend using slicing and concatenation for shifts and rotates. There are issues with the operators (sra etc) and, as you can see, using slicing and concatenation gives you complete control.

Upvotes: 6

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