Tomer Polski
Tomer Polski

Reputation: 41

VHDL shift_right number

I want to divide a number by 512 meaning that I need to shift it by 9. For example in my code I want to take the number 26 in binary form to multiply by 100 and then divide it by 512. But instead of dividing by 512 all I need to do is to shift right 9 times the number 26*100. But when I do the shift_right command I get the following error:

Error (10511): VHDL Qualified Expression error at Multiplier_VHDL .vhd(34): SHIFT_RIGHT type specified in Qualified Expression must match std_logic_vector type that is implied for expression by context

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Multiplier_VHDL is
    GENERIC (
        display_resolution : INTEGER := 23; -- counter to get to the lowest frequency
        display_counter: INTEGER := 8);     -- counter to get to 97KHz frequency

    port (
        Nibble1 : in std_logic_vector(display_counter downto 0) := "000011010"; -- 26 in binary form
        Nibble2 : in std_logic_vector(display_counter downto 0);
        Result: out std_logic_vector(17 downto 0));
end entity Multiplier_VHDL;

architecture Behavioral of Multiplier_VHDL is
    signal number : unsigned(display_counter downto 0) := "001100100"; -- 100 in binary form

begin
    Result <= std_logic_vector(unsigned(Nibble1) * unsigned(number));
    Result <= (shift_right(unsigned(number), display_counter + 1));

end architecture Behavioral;

Upvotes: 0

Views: 1646

Answers (1)

Russell
Russell

Reputation: 3455

shift_right returns either unsigned or signed, depending on what you give it. So you're trying to write an unsigned to a std_logic_vector (Result is of type std_logic_vector).

Also, number is already of type unsigned so there's no need to cast it to unsigned again.

But I give you +1 point for using numeric_std rather than std_logic_arith.

Upvotes: 1

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