CODEWITHSUNDEEP
vhdl
spiderplant0
spiderplant0

Reputation: 3952

How to add std_logic using numeric_std

Using numeric_std and vhdl93, I cant seems to figure out how to add a std_logic signal to a std_logic_vector.

library ieee;
use ieee.numeric_std.all;

signal in_a, out1: std_logic_vector(3 downto 0);
signal s1 : std_logic;

out1 <= std_logic_vector(signed(in_a) + s1);

Upvotes: 4

Views: 13504

Answers (1)

user1155120
user1155120

Reputation: 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity add_std_logic is
end entity;

architecture foo of add_std_logic is
   signal in_a, out1: std_logic_vector(3 downto 0);
   signal s1 : std_logic;
   signal s1v:  std_logic_vector(0 to 0);
begin

    s1v <= (others => s1);

    out1 <= std_logic_vector(signed(in_a) + signed(s1v));

end architecture;

architecture fum of add_std_logic is
   signal in_a, out1: std_logic_vector(3 downto 0);
   signal s1 : std_logic;
   subtype s1v is  std_logic_vector(0 to 0);
begin

    out1 <= std_logic_vector(signed(in_a) + ( s1 & ""));

end architecture;

And of course you could move in_a, s1 and out1 to the port.

Upvotes: 5

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