How to create VHDL testbench for schematic?

Question

I have simple VHDL module test

entity test is 
 port( 
  clk: in std_logic;
  test_out: out std_logic
  ); 
end test;  

architecture Behavioral of test is
begin 
main: process(clk)
variable tmp_buffer : std_logic:='0';
begin
if (rising_edge(clk) and tmp_buffer='0') then
    test_out<='1';
    tmp_buffer:='1';
end if;
if (rising_edge(clk) and tmp_buffer='1') then
    test_out<='0';
    tmp_buffer:='0';
end if;
end process;
end Behavioral;

Created simple schematic

and user constraints file too(Spartan-3 XC3S200):

NET "clk_port" LOC = "C5";
NET "test_out_port" LOC = "B5";

Created testbench for schematic(!)

ENTITY main_main_sch_tb IS
END main_main_sch_tb;
ARCHITECTURE behavioral OF main_main_sch_tb IS 

   COMPONENT main
   PORT( clk_port   :   IN  STD_LOGIC; 
          test_out_port :   OUT STD_LOGIC);
   END COMPONENT;

   SIGNAL clk_port  :   STD_LOGIC;
   SIGNAL test_out_port :   STD_LOGIC;

BEGIN

   UUT: main PORT MAP(
        clk_port => clk_port, 
        test_out_port => test_out_port
   );

    clk_port_proc : process 
                 begin 
                 clk_port <= '0'; 
                 wait for 10 ns; 
                 clk_port <= '1'; 
                 wait for 10 ns;  
             end process;

-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN
      WAIT; -- will wait forever
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;

Here's my project structure

But I am still getting wrong results. test_out_port should be changed with clock process.

I couldnt find good tutorial, so maybe its too dumb, but give me some help

Answer 1

It was dumb mistake with 'if' statements.

if (rising_edge(clk) and tmp_buffer='0') then
        test_out<='1';
        tmp_buffer:='1';

else if (rising_edge(clk) and tmp_buffer='1') then
test_out<='0';
tmp_buffer:='0';
end if;
end if;