CODEWITHSUNDEEP
vhdl
user3000482
user3000482

Reputation: 205

Trying to leftshiftlogical (sll) in VHDL for logic_vector. Getting error["found '0' definitions of operator "sll"]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity leftshift is
    Port ( Din : in  STD_LOGIC_VECTOR (31 downto 0);
           Dout : out  STD_LOGIC_VECTOR (31 downto 0));
end leftshift;

architecture Behavioral of leftshift is

signal t1: std_logic_vector (33 downto 0);

begin
        t1 <= Din sll 2;
    Dout <= t1(33 downto 2)

end Behavioral;

This is my code, but I don't know why I'm getting the error.

found '0' definitions of operator "sll", cannot determine exact overloaded matching definition for "sll"

I also tried using just Dout <= Din sll 2 but it still doesn't work. Please help me.

Upvotes: 3

Views: 45177

Answers (5)

Halfow
Halfow

Reputation: 77

Lets use a fixed size as it will be easier to follow:
signal a, b : std_logic_vector(7 downto 0);

Shift operators:
b <= a sll 2' eq 'b <= a(5 downto 0) & "00"
b <= a srl 2' eq 'b <= "00" & a(7 downto 2)
sal and sar will care about the sign bit.

Roll Opperators:
b <= a rol 2' eq 'b <= a(5 downto 0) & a(7 downto 6)
b <= a ror 2' eq 'b <= a(1 downto 0) & a(7 downto 6)

http://vhdl.renerta.com/mobile/source/vhd00047.htm

Upvotes: 0

rodrigo
rodrigo

Reputation: 1

Or use:

Dout <= Din((31-2) downto 0) & Din(31 downto (31-2));

Same as sll 2;

My version does not recognize all sll 2, however.

Upvotes: 0

etfa
etfa

Reputation: 189

another way to shift left (on a 16-bit word for example):

VECT <= VECT(14 DOWNTO 0) & '0';

Upvotes: 3

wjl
wjl

Reputation: 7765

As rick pointed out in his answer, you can't do sll on a std_logic_vector until VHDL 2008, which is not (and sadly, may never be) well supported in many existing modern FPGA and ASIC toolchains.

One easy workaround is to convert to the standard unsigned type from ieee.numeric_std, do the shift, then convert back to std_logic_vector

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- use IEEE.STD_LOGIC_UNSIGNED.ALL; -- remove this non-standard package
...
        t1 <= std_logic_vector(unsigned(Din) sll 2);

Upvotes: 2

rick
rick

Reputation: 1646

The shift operators (sll included) are defined for std_logic_vectors in VHDL 2008. If you want to use them, just tell your compiler that you are working with this version of VHDL.

Apart from that, there is one mistake in your code: you are trying to assign a 32-bit value to a 34-bit signal (on line t1 <= Din sll 2;). This can be fixed by changing the offending line to t1 <= (Din sll 2) & "00";

Other than that, there is nothing wrong with your code. I ran it through Modelsim Altera SE 10.1b and it compiles and works correctly. Can you tell us what tool version are you using?

Finally, here is a cleaner version of your code, without any auxiliary signals.

library ieee;
use ieee.std_logic_1164.all;

entity shift_left_by_two is
    port ( 
        Din: in std_logic_vector(31 downto 0);
        Dout: out std_logic_vector(31 downto 0)
    );
end;

architecture behavioral of shift_left_by_two is
begin

    Dout <= Din sll 2;

end behavioral;

Upvotes: 1

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