CODEWITHSUNDEEP
vhdlhdlmoving-average
user3008991
user3008991

Reputation: 53

continuous averaging using VHDL

I have a question related to VHDL programming. I want to calculate the continuous average. My example code is:

process (clk, reset)
begin
    if (reset = '1') then 
        state<=idle;
        out-val=0;
    elsif(rising_edge(clk)) then
        case state is

            when idle =>
                if req='1' then 
                    state= out-1;
                end if;

            when out-1 =>
                if done='1' then
                    out-val<=data-in (11 downto 0);
                    state <= done-st;
                endif;

            when done-st =>
                ack <='1';
                state <= idle;

            when others =>
                state <= idle;
        end case;
    end if;
end process;

On every positive edge of clock, the value of "out-val" changes. I want to continuously take the average of "out-val". I want to take average of 32 values continuously. Is there a way where I can take average of 32 values continuously till the clock is running. Kindly let me know how can I do that. You can modify the above code as well.

Many Thanks,

Upvotes: 2

Views: 2094

Answers (2)

ytukel
ytukel

Reputation: 53

Create 32 tap FIR filter whose coeffients are 1/32[1, 1,..... 1]

Upvotes: 0

Russell
Russell

Reputation: 3465

Keep a running total of the 32 values. You can keep a running total by having a signal that has the total count. On each clock cycle, you need to add-in the newest value and subtract-out the oldest value. This means that you need to create a large shift-register or FIFO to keep track of the previous 32 values so you can remove them in order.

Then to get the average just do a shift-right to divide by 32.

Upvotes: 1

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