CODEWITHSUNDEEP
vhdl
A. Kieffer
A. Kieffer

Reputation: 372

Average operation on signed signals in VHDL

I'm trying to calculate the average of a signal on 4 consecutive values. This signal is signed and I'm really not sure about the right calculation to do.

SIGNAL my_signed_signal : std_logic_vector(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL average_sum      : signed(17 DOWNTO 0) := (OTHERS => '0');
SIGNAL average_result   : signed(15 DOWNTO 0) := (OTHERS => '0');

...

-- within my process

average_sum <= average_sum + signed(my_signed_signal); -- loop 4 times

...

average_result <= average_sum(17 DOWNTO 2);   -- how I finally get the result (div by 4)

I am aware that this should work for unsigned signals but I'm pretty sure it doesn't for signed ones because of the signed bit. Yet I don't really know what to change. Does anyone have an idea?

Upvotes: 0

Views: 564

Answers (1)

Matthew
Matthew

Reputation: 13987

Yes, it works for signed types, too.

Upvotes: 1

Related Questions