Reputation: 7556
A great feature of SystemVerilog is inheritance, which AFAIK is limited to classes.
I was wondering if there is a way to mimic inheritance and overloading for interfaces.
For example, suppose interface2 has all signals defined in interface1 pluse sig1001 and modport2. What is the best way of defining interface2 without rewriting everything?
interface interface1;
logic sig1;
...
logic sig1000;
modport modport1(....);
task task1;
...
endtask
endinterface
interface interface2;
logic sig1; //similar to interface1
...
logic sig1000; //similar to interface1
logic sig1001;
modport modport1(....); //similar to interface1
modport modport2(....);
task task1; //similar to interface1
...
endtask
endinterface
I need it to be synthesizable. My goal is not to maintain several interfaces as my code evolves I was thinking of defining a parameter and use if/generate. Any ideas are welcome.
Upvotes: 3
Views: 2388
Reputation: 42623
There is no way to compose a SystemVerilog interface
from other interface
s either by using inheritance or encapsulating them hierarchically. The only way to achieve something similar is to put sections of the interface
in separate files and `include
them as needed.
If you need to do this for a testbench, then you are better off using classes instead.
Upvotes: 2
Reputation: 7573
Even if you do parameters and generate statements inside, this still isn't inheritance. Every specialization of such a parameterized interface creates an own type which is not compatible with another type, i.e.:
interface some_interface #(int some_parameter = 1);
//...
endinterface
some_interface #(2) intf1;
virtual some_interface vif; // per default some_parameter is 1
vif = intf1; // this is illegal because some_interface #(1) and some_interface #(2) are not type compatible
If your idea is to use parameterized ifs in classes, then you're only bet is to define the classes themselves as parameterized.
Upvotes: 0