CODEWITHSUNDEEP
oopverilogsystem-verilog
Karan Shah
Karan Shah

Reputation: 1992

Inheritance & Virtual Interface in systemverilog?

Multiple inheritance is very general OOPS concept, then why it is not implemented in systemverilog and only single inheritance is allowed?

2nd why interfaces are not allowed inside class? Is it because of storage implementation like dynamic storage in class and static in modules, programs, interface?

Upvotes: 0

Views: 1334

Answers (1)

dave_59
dave_59

Reputation: 42623

This really should be two separate posts for your two distinct questions. Unfortunately the keyword interface will be used to answer both of them with entirely separate meanings.

I wrote a 2010 DVCon paper describing some of the reasons that multiple inheritance was not in the original SystemVerilog LRM, and possible solutions. SystemVerilog 1800-2012 did add multiple interface class inheritance and here is a link to a good description of that feature. This use of the keyword interface as a kind of class has nothing to do with the interface in your 2nd question.

You are mostly correct about why interface instances are not allowed in classes. An SV interface is very similar to the design elements module and program that are instances of hierarchical containers. During the process of elaboration, these containers get flattened out before simulation begins. Class instances are only constructed at run-time by executing procedural code.

The elaboration process is particular to hardware description languages and is part of the the code generation and replication process. It is also what allows you to hierarchically reference signals throughout the design without the use of pointers. Class objects on the other hand, are only referenced through dynamically created handles.

Upvotes: 4

Related Questions