CODEWITHSUNDEEP
vhdl
basma
basma

Reputation: 27

what should i do with that vhdl design?

i have a vhdl design measure the distance between two samples (inputs), d(s1,s2). and i want to ask a question

if i have 4 samples such as [ s1,s2,s3,s4 ] and i want to get the distances between every two samples, then i would have d(s1,s2),d(s1,s3),d(s1,s4),d(s2,s3),d(s2,s4)and d(s3,s4). what should i do 1 or 2

1- should i repeat that module 6 times and i would have 6 component of it connected together to get the 6 distances between every sample and the other ...or

2- should i use that module one time and store the distance in register and reset the module then measure the distance between the next two samples and store the the result in another register again and so on....

because i will need the distances result for sum them all to find their mean, max value from them and std deviation .

thanks for help.

Upvotes: 1

Views: 73

Answers (1)

user1818839
user1818839

Reputation:

Either.

Assuming this module is an entity with input and output ports, there are two basic ways you can use it, as you suggest :

  1. Instantiate as many copies of it as you need and wire the inputs and outputs up directly.
  2. Instantiate it once, with something like a state machine to sequence the inputs and outputs through the single entity, and store each output in registers (or an array) until you have them all ready.

The first approach is simplest and fastest as it performs all 6 calculations in parallel.

The second approach uses approximately one sixth of the hardware (plus the state machine, input multiplexers and output storage).

Synthesise the entity, see how fast it is and how large, then decide which approach best matches your goals, including the size of your FPGA.

Upvotes: 3

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