CODEWITHSUNDEEP
vhdl
rmarti89
rmarti89

Reputation: 3

Q: VHDL Implementation of 2 simple funcitons

I'm looking to implement the functions y = a and b; y = (a or b) and (c or d).

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.NUMERIC_STD.ALL;


entity task1_tb is
--  Port ( ); end task1_tb;

architecture Behavioral of task1_tb is

--declaring the component   component task1
      Port ( a : in STD_LOGIC;
      b : in STD_LOGIC;
      y : out STD_LOGIC);   end component;

      signal y,a,b:     std_logic;
      signal counter:       unsigned(1 downto 0):="00";

begin       
    uut: task1 port map(a => a, b => b, y => y );

end Behavioral;

How can I assign a (bit 1) and b (bit 2) so it will test ever possible value and make a 20ns delay between each combination? I've been trying to learn VHDL these past two days for a school project and not even sure if what I have is right.

Upvotes: 1

Views: 236

Answers (1)

QuantumRipple
QuantumRipple

Reputation: 1159

You're looking to use a wait for <duration> in your stimulus process.

process
begin
   for i in 0 to 2**2-1 loop --2**(number of input bits)-1
      (a, b) <= to_unsigned(i,2);
      wait for 20 ns;
   end loop;
   wait;
end process;

Credit to user1155120 for refinements.

Upvotes: 2

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