CODEWITHSUNDEEP
arraysif-statementvhdloperands
Hitokage
Hitokage

Reputation: 803

VHDL Array element in if-statement

This is my first work with VHDL so it's surely something basic but just don't know what to do.

I have this code:

--this is in the architecture segment
type my_code is array(0 to 15) of integer;
signal code: my_code;
....
--here I use the array
code(count) <=0; --I save a value into the array on position defined by the count variable
if (code(0) = '0') then --fail line (want to do something if the first element is 0)
--do something
end if;

The compiler stops me because "can not have such operands in this context". The problem is on line with the if statement. What is wrong with that?

I am basically working on a digital lock like you write a code and it will open or remain closed if the code is wrong so I just want to check the array of pressed keys if the code in there is right.

Sorry for bothering but I just don't get it. Thanks and have a nice day ^^

Upvotes: 0

Views: 1882

Answers (2)

Philippe
Philippe

Reputation: 3730

You have an array of integers, so code(0) must be an integer. You cannot compare an integer to character literal '0'.

Either check for code(0) = 0 or redefine your array as type my_code is array(0 to 15) of bit; You can use bit or std_logic, or any other type that has '0' as valid element.

Upvotes: 1

user1155120
user1155120

Reputation:

code is an array of integers. You are trying to compare it to a character literal '0', which has no interpretation as an enumeration literal in the context of integers. Try 0 instead.

Also the parentheses surrounding the expression (code(0) = '0') are redundant.

There is no operator defined to compare an integer to a type represented by a character literal in the code context (which you haven't display in your example, not having any context clauses visible nor other declarations).

The "=" equality operator to use is selected by comparing the input operands and result type. There is no operator visible by selection providing a left argument of integer and a right argument of some (not known from your code fragment) type represented by the character literal '0' as an enumeration literal.

Operators that can be selected among several possibilities based on operand type are said to be overloaded.

After a bit of Googling and finding the answer to the general question raised by this Xilinx error message to always dwell on the immediate case I found a few places you can look to understand the issue.

Reference texts:

There are two sub sections in IEEE Standard VHDL Language Reference Manual (the LRM, e.g. IEEE Std 1076-2008, -1993), entitled Subprogram overloading (operators on non predefined typed are functions) in the section Subprograms and packages, and The context of overload resolution in the section Scope and visibility.

VHDL: HARDWARE DESCRIPTION AND DESIGN, Lipsett, Schaefer and Ussery, 1989, Kluwer Academic Publishers.

Also Peter Ashenden and Jim Lewis's 3rd Edition of The Designer's Guide to VHDL, Morgan Kaufman, 2008.

The solution can be either expanding or adding a context clause for missing references to overloaded operators or fixing (as in your case) a syntax error. Which of the two can be case specific.

Upvotes: 0

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