CODEWITHSUNDEEP
vhdlverilogsystem-veriloguvmregister-transfer-level
newbie
newbie

Reputation: 4789

How to code scoreboard for out-of-order transactions between golden C model and RTL?

I've a UVM test env where both golden C++ model and RTL are instantiated. In some cases my C++ model and RTL outputs will go out of order as C++ model is not cycle accurate. For in-order outputs, I just have infinite queues in my scoreboard. Whenever I see output in RTL interface, I try to match it with the head of c++ model-output queue. Here the assumption is outputs from c++ model will always come before RTL output as there is no notion of time c++ model.

However things can go crazy and out of order in few scenarios (as an example, arbiter). In that case, what is the standard way to write scoreboard and checking codes in UVM?

Upvotes: 0

Views: 3596

Answers (1)

dwikle
dwikle

Reputation: 6978

Here is a solution assuming transactions can arrive in any order, from either the device under test (DUT) or the behavioral C++ model.

Maintain two queues of observed transactions.

  • Expected -- This will hold transactions from the model
  • Actual -- This will hold transactions from the DUT

When the scoreboard receives a transaction from the DUT or the model, first check if it exists in the other queue. If so, then you found a match. Otherwise add it to the appropriate queue.

So you will have:

  • On receipt of DUT transaction
    • Check the Expected queue for a match
    • If found, remove it from Expected
    • Else, add it to Actual
  • On receipt of model transaction
    • Check the Actual queue for a match
    • If found, remove it from Actual
    • Else, add it to Expected

You should also verify that the queues are empty at the end of the test. And you can add other checks as well depending on your requirements. E.g. if you only expect 1 or 2 items out of order you only look for a match to a depth of 1 or 2 in the other queue.

Upvotes: 1

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