CODEWITHSUNDEEP
vhdl
theGreenCabbage
theGreenCabbage

Reputation: 4845

Implementing an OR gate with for-generate

I have implemented an OR gate with generic parameters, but I am currently having some issues implementing it with a for-generate.

entity OR_gate is
generic( n : natural := 2);
port(x : in std_logic_vector(1 to n);
      z : out std_logic);
end OR_gate;
architecture Behavioral of OR_gate is
begin
    process(x)
    variable temp : std_logic;
    begin
    temp := '0';
    G1: for i in 1 to N loop
        temp := temp or x(i);
    end generate G1;
z <= temp;
end process;
end Behavioral;

I have the G1 parameter which indicates a loop, however as far as that goes, I am lost.

Upvotes: 1

Views: 1771

Answers (1)

Morten Zilmer
Morten Zilmer

Reputation: 15924

It is not a generate (concurrent) loop when made inside a process. In this case it is just a regular loop, with syntax without the generate, thus as:

process(x)
  variable temp : std_logic;
begin
  temp := '0';
  G1 : for i in 1 to N loop
    temp := temp or x(i);
  end loop G1;
  z <= temp;
end process;

An alternative to the process, is to create a function, and then make a concurrent function call in order to generate z, like:

architecture Behavioral of OR_gate is

  function or_reduct(slv : in std_logic_vector) return std_logic is
    variable res_v : std_logic;
  begin
    res_v := '0';
    for i in slv'range loop
      res_v := res_v or slv(i);
    end loop;
    return res_v;
  end function;

begin

  z <= or_reduct(x);

end Behavioral;

Finally, if the tools support the logical reduction operators defined VHDL-2008, then you can simplify it all to:

z <= or x;

Upvotes: 1

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