CODEWITHSUNDEEP
vhdlclockzynq
TheAlPaca02
TheAlPaca02

Reputation: 523

Zybo Zynq-7000 clk in ucf?

I recently bought myself a Zybo Zync-7000 dev board so I could do some schoolwork & fiddling around with it at home, but when I was going to pick out my clock out of my UCF for the first time I came across this.

## Clock signal
#NET "clk"        LOC=L16 | IOSTANDARD=LVCMOS33; #IO_L11P_T1_SRCC_35    
#NET "clk" TNM_NET = sys_clk_pin;
#TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 125 MHz HIGH 50%;

I know I probably just have to take the first line to get my clk signal working but what is the rest for? Or am I mistaken and do I need all of it?

We got different hardware back in school and its a bit more straightforward there.

Thanks in advance.

Upvotes: 0

Views: 1725

Answers (1)

QuantumRipple
QuantumRipple

Reputation: 1139

I assume you are using ISE and not the new Vivado since only ISE uses UCF constraint files.

## Clock signal

This line is a comment about what the following lines pertain to.

#NET "clk"        LOC=L16 | IOSTANDARD=LVCMOS33; #IO_L11P_T1_SRCC_35

This line specifies which physical pin (LOC=L16) on the FPGA the clock input (the input net named "clk" in the VHDL top level) from off-chip is connected to. It also specifies that the signal uses low voltage CMOS 3.3v signaling.

#NET "clk" TNM_NET = sys_clk_pin;

This just assigns a timing name to the net. For timing specific constraints, the timing name will be used instead of the (VHDL internal) net name.

#TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 125 MHz HIGH 50%;

This specifies that the timing of "sys_clk_pin" (resolves to the VHDL net "clk") should have a frequency of 125 MHz and a duty cycle of 50%. The tool needs to know this to determine how to route the signals without violating flip flop setup or hold times. The name "TS_sys_clk_pin" is just an identifier for this particular constraint.

Properly constraining a design is very important when you are near to filling up a part or if you want to run it at a higher clock speed. You can find a great wealth of information in the Xilinx constraint guide for ISE: https://www.xilinx.com/content/dam/xilinx/support/documents/sw_manuals/xilinx14_7/cgd.pdf

If you don't give your design timing constraints, the tools will typically throw a warning about the lack of constraints and it will tell you how fast you can run it at the end without causing errors. Timing constraints for the clocks are the most important. You typically only need other timing constraints on synchronous inputs and cross clock boundaries.

Note that all 4 lines are, in fact, currently commented out (prepended with a #). If you want to use the 3 functional lines, you need to remove the comment designation.

Upvotes: 2

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