CODEWITHSUNDEEP
verilog
user3751971
user3751971

Reputation: 49

Syntax error: Port is not defined Verilog file

module ram_1_verilog(input EnA,input EnB,
  input WeA, input WeB,
  input Oe,
  input clk);
 
LINE :25   input [7:0] Addr_a;      //Error
LINE :26   input [7:0]Addr_b;       //Error
LINE :27   input reg [7:0] dout1;   //Error
LINE :28   output reg [7:0] dout_2; //Error
    
reg [7:0] ram [255:0];
    
always @(posedge clk)
begin
  if(EnA == 1 && WeA == 1) begin 
LINE 35  ram(Addr_a) <= dout1;      //Error 
  end
end
    
always @(posedge clk)
begin
  if(EnB == 1 && WeB == 0) begin
  LINE : 44 dout_2 <= ram(Addr_b);  //Error
  end
end
endmodule

Errors:

Syntax error near "<=". line 35
Line 25: Port Addr_a is not defined Verilog file C:/Documents and Settings/verilog_examples/ram_1_verilog.v ignored due to errors
Line 25: Port declaration not allowed in ram_1_verilog with formal port declaration list
Line 26: Port Addr_b is not defined
Line 26: Port Addr_b is not defined
Line 26: Port declaration not allowed in ram_1_verilog with formal port declaration list
Line 27: Port dout1 is not defined

Line 27: Non-net port dout1 cannot be of mode input
Line 27: Port declaration not allowed in ram_1_verilog with formal port declaration list
Line 28: Port dout_2 is not defined
Line 28: Port declaration not allowed in ram_1_verilog with formal port declaration list
Line 35: dout1 is not a task

Line 44: ram is not a function.
Line 44: ram expects 0 arguments.
Line 44: Cannot assign an unpacked type to a packed type.

I'm working on a dpram, but I'm getting errors in Verilog. Please help me figure out the error.

Upvotes: 0

Views: 6341

Answers (2)

Qiu
Qiu

Reputation: 5751

  1. Lines 35 and 44 - you've made twice the same mistake, explained to you by Tim.
  2. Lines 25-28 are flagged, because Addr_a, Addr_b, dout1 and dout_2 are not declared in port declaration list and then are defined as input/output.

Upvotes: 2

Tim
Tim

Reputation: 35923

One issue I see is that you are attempting to do array selection with parenthesis, when it should use square brackets:

Change from:

LINE 35         ram(Addr_a) <= dout1;       // error

to:

LINE 35         ram[Addr_a] <= dout1;

I don't see any errors on line 25-28, not sure why those are being flagged.

Upvotes: 2

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