CODEWITHSUNDEEP
verilogsystem-verilogtest-bench
user3540595
user3540595

Reputation: 21

Ring Oscillator code always shows Z for the output

I want to write code in Verilog for a Ring Oscillator.

Here is my code:

module RingOsci(enable, w1, w2, w3);
    input enable;
    output w1, w2, w3;
    wire w4;

    and (w4, enable, w3);
    not #2(w2, w1);
    not #2(w3, w2);
    not #2(w1, w4);
endmodule

But, W_i is always Z.

Here is my test bench:

module RingOsciTB();
    reg en;
    wire out1, out2, out3;

    initial begin
        en = 1'b0;
        #20
        en = 1'b1;
    end
endmodule

How can I change the Z value and enable the Oscillator?

Upvotes: 1

Views: 10807

Answers (1)

toolic
toolic

Reputation: 62105

You need to add an instance of your design module in your testbench. For example:

module RingOsciTB();
    reg en;
    wire out1, out2, out3;

RingOsci dut (
        // Inputs:
    .enable  (en),
        // Outputs:
    .w1      (out1),
    .w2      (out2),
    .w3      (out3)
);

    initial begin
        en = 1'b0;
        #20
        en = 1'b1;
    end
endmodule

Upvotes: 5

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