CODEWITHSUNDEEP
bit-manipulationverilogsystem-verilog
Vincent Chan
Vincent Chan

Reputation: 13

Verilog module outputs z's

I'm trying to make a parameter and module to AND two numbers together and return a result. However, I seem to be having troubles. My code is as follows:

module main;
   reg signed [3:0] x;
   reg signed [3:0] y;
   wire [3:0] out1;
   ander #(.L1(4)) andd(.in1(x), .in2(y), .out(out1));

   initial begin
       x = 4'b0111;
       y = 4'b1110;
       $display("%b", out1);
       $finish;
   end
endmodule
    
module ander        #(parameter L1 = 8)
                        
                     (input [L1-1:0] in1,
                        input [L1-1:0] in2,
                        output wire [L1-1:0] out);
                      
      assign out = in2&in1;
endmodule

When I try to run this, the output is "zzzz." Am I doing something wrong?

When I change it to

$display("%b", x&y);

it seems to display just fine.

Do you have any recommendations?

Upvotes: 1

Views: 1267

Answers (2)

Greg
Greg

Reputation: 19114

Add a little delay before the $display

initial begin
  x = 4'b0111;
  y = 4'b1110;
  #1; // <-- Add a little delay
  $display("%b", out1);
  $finish;
end

Verilog does one operation at a time. When inside a procedural block, it will execute every operation within the block until it hits a blocking statement or finishes. In Your case, the assign statement didn't have time to react to the changes in x and y before the initial block called $display and $finish.

Upvotes: 2

toolic
toolic

Reputation: 62073

If you want a deterministic output, add some delay before your $display:

   initial begin
       x = 4'b0111;
       y = 4'b1110;
       #1;
       $display("%b", out1);
       $finish;
   end

This prints 0110.

Upvotes: 1

Related Questions