CODEWITHSUNDEEP
verilog
Lerbi
Lerbi

Reputation: 225

How does Verilog interpret multiplication by a single bit?

I have a conditional 2-bit variable coming in. Based off its value, the current value is either incremented or decremented. By that, I mean:

module verilog_block(clk, cond, incr, curr_val)
input clk;
input [1:0] cond;
input [5:0] incr;
output reg [5:0] curr_val;

always @ posedge(clk)
begin
curr_val <= curr_val + (!cond[1] - cond[1]) * incr * cond[0];
end

endmodule

Sorry if I made any mistakes, I haven't checked this specific code, as I am just trying to illustrate my question. If cond[0]==0, I don't want curr_val to change (irrespective of cond[1]). If cond[1]==1, I want curr_val to reduce by incr, and if cond[1]==0, I want curr_val to increment by incr.

I think this works, theoretically, but my goal is to expand this into a much larger code. Therefore, it needs to be optimized. I know that the * operator can be slow and require a lot of resources, but I am not sure if that applies to the case of multiplication with only one bit.

If you can spot a way to make this code optimized for area, please let me know. Thanks a lot.

Upvotes: 0

Views: 267

Answers (1)

dave_59
dave_59

Reputation: 42698

Any good synthesis tool will optimize multiplication where it can, especially when it involves multiplication by zero or any power of 2. But you've created a very hard to read operation. Why not write it the way you said it:

always @ posedge(clk)
  begin
     if (cond[0]==1) 
       curr_val <= curr_val + (cond[1]==1) ? -incr : incr;
end

Upvotes: 2

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