CODEWITHSUNDEEP
verilog
Spice
Spice

Reputation: 31

How to address individual bits in an input when calling a module from another module?

I am trying to address a variety of bits in a 24-bit input from my top module to an xor module I created, but I need some help knowing how to format the code for it. This code works for my first case I need, however I need to assign bits 5, 10, 15, 20, and the value of 1 to the data bits 0-4 respectively in the XOR module. Specifically I want xorOut[1] to be xor of Data[5, 10, 15, 20] and 1, xorOut[2] to be xor of Data[9, 13, 17, 21] and 1, xorOut[3] to be the xor of Data[8, 11, 19, 22] and 1. I would like to know if that is possible to assign individual data bits in that manner and not consecutively. I am unsure how to do something like this, so any help would be appreciated.

module XOR(
    input [4:0] Data,
    output Out
);
    
    assign Out = Data[0] ^ Data[1] ^ Data[2] ^ Data[3] ^ Data[4];
endmodule

module twobit(
    input [24:0] Data,
    output [24:0] Errors
    );  
    
    wire [4:0] xorOut;
    XOR u1 (.Data(Data[4:0]), .Out(xorOut[0]));
    
endmodule

Upvotes: 1

Views: 496

Answers (1)

toolic
toolic

Reputation: 62073

You can use the concatenation operator ({}) to create a bus signal from individual bits. For example:

module twobit(
    input  [24:0] Data,
    output [24:0] Errors
);  
    
    wire [4:0] xorOut;
    XOR u1 (.Data(Data[4:0]), .Out(xorOut[0]));
    XOR u2 (.Data({Data[5], Data[10], Data[15], Data[20], 1'b1}), .Out(xorOut[1]));
    XOR u3 (.Data({Data[9], Data[13], Data[17], Data[21], 1'b1}), .Out(xorOut[2]));
endmodule

Upvotes: 1

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