CODEWITHSUNDEEP
moduleverilog
ItM
ItM

Reputation: 331

Ring Oscillator in Verilog using generate

I'm looking to create a ring oscillator in Verilog, using inverters and generate. Here's what I've tried so far:

module ringOsc(outclk);
    parameter SIZE = 8; // This needs to be an even number
    output outclk;
    wire [SIZE : 0] w;

    genvar i;
    generate
        for (i=0; i<SIZE; i=i+1) begin : notGates
            not notGate(w[i+1], w[i]);
        end
        not notGateFirst(w[0], w[SIZE]);
    endgenerate

    assign outclk = w[0];

endmodule

This will be loaded onto an FPGA and the frequency of oscillation will be measured (of course with more than 9 inverters). Is this correct or am I missing something? Any help would be appreciated.

Upvotes: 0

Views: 2783

Answers (1)

Oldfart
Oldfart

Reputation: 6259

For a ring oscillator you need to have a delay. The not gates you are using have no such delay in simulation as they are ideal models.

Simplest is to add a delay to the gates:

not #(5,5) notGate(w[i+1], w[i]);

not #(5,5) notGateFirst(w[0], w[i]);

Also it is good practice to have en enable: one of the gates is a NAND gate.

You also need to tell the tool not to optimise your ring oscillator away. For that you have to look at the synthesis tool of your FPGA, especially the constraints settings to prevent logic optimization. Defining the intermediate nets as 'keep' might work.

Upvotes: 1

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