CODEWITHSUNDEEP
parsingsyntaxverilog
Aragon
Aragon

Reputation: 1551

Can we give range at named port declaration and not at time of identifier declaration in verilog

module some ( .a( i [2:0] ), .b( j [0:5] ) )
    input i;
    output j;
endmodule

Is above declaration valid or we have to give range at input [2:0] i; also.

Upvotes: 0

Views: 314

Answers (2)

Jared Davis
Jared Davis

Reputation: 569

You must separately declare i and j with suitable ranges.

When you use the .name(expression) syntax in a port list, you are:

  • setting the external name of the port to name, and
  • explaining how to connect it to the declared ports of the module

For instance, consider a module like this:

module some (.a(i[2:0]), .b(i[7:3]))
  input [7:0] i;
endmodule

Here the module some will have two externally visible ports:

  • a 3-bit port called a, and
  • a 5-bit port called b,

So a valid instance of this module could look like:

some mysome (.a(3'b110), .b(5'b11001));

Internally, these bits will get mashed together to create i == 8'b 11001_110.

For more information see Section 12.3.1 of the Verilog-2005 standard, or Section 23.2.2.1 of the SystemVerilog-2012 standard (which are both very similar, and both have examples.)

Upvotes: 2

Morgan
Morgan

Reputation: 20514

I think your confusing the syntax, in the example you .a which refers to a port called a which does not exist in your code. Just to clarify:

Declaring a module

module some (
    input  [2:0] i,
    output [5:0] j
);
endmodule

Instancing a module:

reg  [2:0] a;
wire [5:0] b;
module_name instance_name (
 .i( a [2:0] ),
 .j( b [5:0] )
);

Upvotes: 0

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