Reputation: 571
my problem is that I have an int_array generic in a VHDL entity and I want to set it from my SV tb. Which is the correct SV data type to do it? I tried several possibilities but no one of them was correct. Thanks in advance.
Upvotes: 1
Views: 1961
Reputation: 7573
It's not possible to say exactly. Because the interface between VHDL and SystemVerilog isn't specified in any way, it's up to the simulator vendors to implement it in whatever way they see fit. You'll have to ask your EDA vendor if what you want is possible and if so, which data type you need to use.
Since you didn't provide any code, I'll just have to speculate that you had to define your array type before using it as a generic (as otherwise it doesn't compile):
package my_types_pkg is
type my_array_t is array (0 to 2) of integer range 0 to 255;
end package my_types_pkg;
This is probably how your DUT looks like:
entity dut is
generic (
int_array : my_array_t
);
end dut;
architecture dummy of dut is
begin
end dummy;
Because we've had to define a new type there, Questa requires us to import the type definition into the SystemVerilog world. This is where it gets proprietary. The way Mentor Graphics chose to do this is by compiling the VHDL package with the -mixedsvvh
switch:
vcom -mixedsvvh dut.vhd
It's essential that the type is defined inside a VHDL package otherwise it won't get exported. Inside your SystemVerilog file you can just define a localparam
of the my_array_t
type and use that for your instantiation:
module top;
localparam my_types_pkg::my_array_t my_array = '{ 1, 2, 3 };
dut #(my_array) dut_inst();
endmodule // top
In the code above my_types_pkg
is the package defined in VHDL, which was exported to SV with the -mixedsvvh
switch.
Now comes the sad part. This doesn't work for me. Even though the types match, vsim
still complains that the generic isn't valid. This answer should help you get started, though (what to search for in the docs, for example). Also try taking this case to Mentor Graphics support.
Upvotes: 2