CODEWITHSUNDEEP
verilog
Ali Hatami
Ali Hatami

Reputation: 1

describing clocked SR Latch with verilog

I'm trying to describe a clocked SR-Latch with NAND gates in Verilog. However, when I simulate it, all the outputs become Z, and I don't know why.

Verilog code and the testbench:

module CLOCKED_SR(input clk, s, r, output q, qbar);
  wire i, j;
  nand #20 (s, clk, i);
  nand #20 (r, clk, j);
  nand #20 (qbar, j, q);
  nand #20 (q, i, qbar);
endmodule

module Q1_test();
  reg clk, s, r;
  wire qbar, q;
  CLOCKED_SR T_SR(clk, s, r, qbar, q);
  initial begin
    #20 clk = 1;
    #50 s = 0; r = 0;
    #50 s = 0; r = 1;
    #50 s = 1; r = 0;
    #50 $stop;
  end
endmodule

Upvotes: 0

Views: 1553

Answers (1)

Unn
Unn

Reputation: 5108

When using gate primitives in Verilog, the output is always the first value in the instantiation list. So you have in the first level of NAND gates i and j as inputs, not outputs.

You need to make sure the output of the gate is first:

module CLOCKED_SR(input clk, s, r, output q, qbar);
  wire i, j;
  nand #20 (i, clk, s);
  nand #20 (j, clk, r);
  nand #20 (qbar, j, q);
  nand #20 (q, i, qbar);
endmodule

Upvotes: 2

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