CODEWITHSUNDEEP
verilogsystem-verilogdigital-logicflip-flop
Ju Bc
Ju Bc

Reputation: 173

SystemVerilog: S-R Latch doesn't work correctly

Here is my gate-level description of an S-R latch:

module SR_Latch_Nand(input S, R, C, output Q, QB);
  wire s1, r1;
  nand #8 n1(r1, R, C);
  nand #8 n2(s1, S, C);
  nand #8 n3(QB, R, Q);
  nand #8 n4(Q, S, QB);
endmodule

and here is test bench for this S-R latch:

module SR_Latch_Nand_TB();
  logic s, r, clk;
  wire q, qb;
  SR_Latch_Nand sr(s, r, clk, q, qb);
  initial begin
    s = 0; r = 0; clk = 0;
    #100 s = 1;
    #100 clk = 1;
    #100 clk = 0;
    #100 clk = 1;
    #100 s = 0;
    #100;
  end
endmodule

When I check waverform, value of Q is X at most of the times. Other times it's mostly incorrect. I've tried to preset values of Q, QB but it still doesn't seem to work.

So can you tell what's the problem with this code?

Upvotes: 0

Views: 945

Answers (2)

Kiran
Kiran

Reputation: 21

The code of SR_Latch_Nand is wrong. You missed to use the s1 and r1 for the output NAND gates n3 and n4. Corrected SR latch module should be:

module SR_Latch_Nand(input S, R, C, output Q, QB);
  wire s1, r1;
  nand #8 n1(r1, R, C);
  nand #8 n2(s1, S, C);
  nand #8 n3(QB, s1, Q);
  nand #8 n4(Q, r1, QB);
endmodule

Upvotes: 1

dave_59
dave_59

Reputation: 42788

The problem is with your testbench. If both r and s are active low, make sure your test bench test only one of them active low.

Upvotes: 0

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