CODEWITHSUNDEEP
verilog
Karan Gupta
Karan Gupta

Reputation: 11

Why is the SR latch output always X?

I am implementing SR latch without clock signal using Verilog. I am trying with the code given below, but I am getting the value of Qb as X. Please help me.

// design.v file
module sr_latch(q,qb,s,r);// module declaration
  input s,r; 
  output q,qb;
  assign qb=~q;
  nand (q,s,qb);
  nand (qb,r,q);
endmodule

// testbench.v file
module stimulus;
  reg set,reset;
  wire Q,Qb;
  sr_latch mylatch(Q,Qb,set,rest);
  initial
    begin
      $dumpfile("dump.vcd");
      $dumpvars;
      $monitor($time,"set=%b,reset=%b,Q=%b,Qb=%b\n",set,reset,Q,Qb);
         set=0; reset=0;
      #5 set=0; reset=1;
      #5 set=1; reset=0;
      #5 set=1; reset=1;
    end
endmodule

Result:

               0set=0,reset=0,Q=1,Qb=x

               5set=0,reset=1,Q=1,Qb=x

              10set=1,reset=0,Q=x,Qb=x

              15set=1,reset=1,Q=x,Qb=x

Upvotes: 1

Views: 148

Answers (1)

toolic
toolic

Reputation: 62236

There are 2 errors in your code.

In your design file, you have 2 drivers for the qb signal, but you should only have 1. You should delete the following line:

  assign qb=~q;

You have a typo in the testbench; I got a compile warning about this in one of the simulators on edaplayground. You misspelled reset as rest. Change:

sr_latch mylatch(Q,Qb,set,rest);

to:

sr_latch mylatch(Q,Qb,set,reset);

Result:

               0set=0,reset=0,Q=1,Qb=1

               5set=0,reset=1,Q=1,Qb=0

              10set=1,reset=0,Q=0,Qb=1

              15set=1,reset=1,Q=0,Qb=1

Upvotes: 1

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