CODEWITHSUNDEEP
system-verilog
fouadalnoor
fouadalnoor

Reputation: 217

Why can I not store 16 bits in a logic in SystemVerilog?!

I am currently having issues when trying to store a 16bit number coming from the input of my module into one of my logic variables. When I set all the bits high in my test bench I get a value: 0000000000000001. Hope you can help! PS: Sorry, dont know how to insert code on here....

My code is shown below:

http://pastebin.com/cZCYKJqV

Upvotes: 0

Views: 561

Answers (1)

dwikle
dwikle

Reputation: 6978

I think your problem is likely with this line:

regy = (!regy)+1;

regy is a 16-bit value. Using the negation operator (!) on a multi-bit value is equivalent to (value != 0). So for any value of regy other than zero will set regy to 1.

If you are trying to invert all the bits and add 1, you need to use the ~ operator.

Example:

regy = (~regy)+1;

Upvotes: 1

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