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verilogsystem-verilog
Mike
Mike

Reputation: 1319

In SystemVerilog, can events be defined in ports

In Verilog, I know we can't pass "events" between modules. Howe about in System Verilog ? I would like the event "trig" hooking the trigger source blocks "eventGen" and is consumed by the block "eventConsume" Some how I get compilation error

Code:

module propagateEvents;

reg clk;
event trig;

initial
begin
    clk = 1'b0;
end

always #10 clk = ~clk;

eventGen eventGen (trig, clk);
eventConsume eventConsume (trig, clk);

endmodule

module eventGen(trigGen, clk);

input clk;
event trigGen;

reg count[3:0];

initial
    count = 0;

always @(posedge clk)
begin
    count = count + 1'b1;
    if (count == 'h8)
        ->trigGen;
end

endmodule

module eventConsume(trigConsume, clk);

input clk;
event trigConsume;

always @(trigConsume)
begin
    $display("Trigger caught");
end
endmodule

Upvotes: 1

Views: 2603

Answers (1)

Greg
Greg

Reputation: 19094

You need to give a port direction; ex. inout event. Working example here. SystemVerilog can also use ref event.

Note that event is not synthesizable. Also reg count[3:0] needs to be reg [3:0] count.

module eventGen(output event trigGen, input clk);
reg [3:0] count;
initial count = 0;
always @(posedge clk)
begin
    count = count + 1'b1;
    if (count == 'h8)
        ->trigGen;
end
endmodule

module eventConsume(input event trigConsume, input clk);
always @(trigConsume)
begin
    $display("Trigger caught");
end
endmodule

Upvotes: 1

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